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CS22250 Data Sheet
Wireless 10BT Controller
1 Introduction
The Cirrus Logic CS22250 Wireless Network Controller enables high speed, 11 Mbps digital wireless data connectivity for wireless Ethernet bridge, access points, and other broadband applications. The CS22250 is a highly integrated single-chip Ethernet bridge solution for wireless networks supporting video, audio, voice, and data traffic. The programmable controller executes Cirrus Logic's WhitecapTM2 networking protocol that provides Wi-FiTM (802.11b) compliance, multimedia and a foundation for quality of service (QoS) applications, and Ethernet to wireless bridging. The device includes several high performance components including an ARM7TDMI RISC processor core, a Forward Error Correction (FEC) codec, and a wireless radio MAC supporting up to 11 Mbps throughput. The CS22250 utilizes state of the art 0.18um CMOS process and is housed in a 208 FPBGA compact package, offering low-lead inductance suitable for highly integrated radio applications. The core is powered at 1.8 V with 3.3V I/O to reduce overall power consumption. In addition, the CS22250 supports various power management modes for host, MAC, baseband, and radio interfaces. The CS22250 is designed to provide integrated low cost IEEE 802.3 standard compliant system solutions. The controller also incorporates a high-speed parallel interface, which can be used to interface with other ASICs (eg: HNPA 2.0 Network controller) to implement a variety of other wireless LAN bridging products. 10 BaseT Ethernet PHY AUI Serial Interface 802.11b compatible 2.4 GHz Digital Radio PHY Transceiver 11 Mbps Wireless Baseband I/F CS22250 Wireless 10BT Controller System Memory SDRAM (Up to 4MB) SRAM (Up to 256KB) Boot ROM/Flash (Up to 1MB)
2.4 GHz Direct Sequence Spread Spectrum
High Speed Parallel Interface
Configuration Interface (USB)
Figure 1. Example System Block Diagram CS22250 Wireless 10BT Controller 1 of 32 www.cirrus.com DS551PP2 Rev. 3.0
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Features
Embedded ARM Core and System Support Logic * High Performance ARM7TDMI RISC processor core up to 77MHz * 4KB integrated, one-way set associative, unified, write through cache * Individual interrupt for each functional block * Two 23-bit programmable (periodic or one-shot) general purpose timers * 8 Dword (32-bits) memory write and read buffers for high system performance * Abort cycle detection and reporting for debugging * ARM performance monitoring function for system fine-tuning * Programmable performance improvement logic based on system configuration. Enhanced Memory Controller Unit * Programmable memory controller unit supporting SDRAM /async SRAM/boot ROM/Flash interface * 16-bit data bus with 12-bit address supporting up to 4MB and up to 103 MHz (100/133MHz SDRAM) * 8-bit data bus with addressing support up to 1MB of boot ROM/Flash * Programmable SDRAM timing and size parameters, such as CAS latencies and number of banks, columns and rows * Flexible independent DMA engines for Ethernet MAC, Digital Radio and External Bus functional units FEC codec * High performance Reed-Solomon coding for error correction (255:239 block coding) * Reduces error probability of a typical 10e-3 error rate environment to 10e-9 * Programmable rate FEC engine to optimize channel efficiency * Low latency, fully pipelined hardware encoding and decoding. Supports byte-wise single cycle throughput up to 77MHz, with a sustain rate of 77MBps * Double buffering (63 Dword read/write buffer) to enhance system performance Digital Wireless Radio MAC * Glue-less interface to 802.11b radio baseband transceiver * 11Mbps data rate * 32 Dword transmit/receive FIFO * Supports clear channel assessment (CCA) Ethernet Interface * IEEE802.3 Ethernet MAC controller * Two independent full-duplex DMA channels transfer between Ethernet interface to system memory * Standard 7-pin serial interfaces to AUI or Twisted Pair 10-BaseT * Standard half-duplex CSMA/CD and full-duplex operation USB Device Configuration Interface * USB 1.1 compliant
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Features and Benefits
Power Management * ACPI compliant * Programmable sleep timer for ARM core and system power management * Independent power management control for individual functional blocks * Supports variable rate radio transmit, receive and standby radio power modes Clock and PLL Interface * Single 44MHz crystal oscillator reference clock * Internal PLL to generate internal and on board clocks Chip Processing and Packaging * 208 FPBGA package and 0.18um state of the art CMOS process * 1.8 V core for low power consumption. 3.3V I/O High Speed Parallel Interface * Multi-purpose 32bit bus for connecting with other high speed devices * Supports operations at 1/2 the speed of the ARM clock (up to 38MHz) * Two independent full-duplex DMA channels transfer between external devices to ARM system memory * Supports one external interrupt pin to the ARM core
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IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFESUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Use of this product in any manner that complies with the MPEG-2 video standard as defined in ISO documents IS 138181 (including annexes C, D, F, J, and K), IS 13818-2 (including annexes A, B, C, and D, but excluding scalable extensions), and IS 13818-4 (only as it is needed to clarify IS 13818-2) is expressly prohibited without a license under applicable patents in the MPEG-2 patent portfolio, which license is available from MPEG LA, L.L.C. 250 Steele Street, Suite 300, Denver, Colorado 80296.
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Functional Description
Figure 2. Block Diagram of Major Functional Units
Memory/Boot ROM Controller Arbiter DMA DMA 7 pin Serial Interface Ethernet MAC w/ DMA Controller Read/Write Buffer
DMA Controller Interrupt controller
System Memory
DMA JTAG/Test Interface
ARM 7TDMI Timer (2) 4KB Cache Radio MAC w /DMA Ctrl Digital Radio Interface
DMA High Speed Parallel Interface Parallel Interface Controller
USB
USB Device Configuration Interface
77MHz System Control Bus
Sleep Timer
FEC codec
Config. Registers
Clock/PLL
Crystal or Oscillator
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3.1
Embedded ARM core and System Support Logic
The processing elements of the CS22250 include the ARM7TDMI core and its associated system control logic. The ARM processor and system controller consist of a memory management unit, 4-KB write through cache controller, 20 IRQ and 4 FIRQ interrupt controller, and 2 general purpose timers. The ARM processor and integrated system support logic provide the necessary execution engine to support a real time multi-tasking operating system, the network protocol stack, and firmware services.
Memory Management UnitThe ARM instructions and data are fetched from system memory per "cache-line" (4/8 - Dwords /Programmable) when caching is turned on. During a cache line fill, critical word data, i.e., the access that caused the miss, is forwarded to the ARM and also written into the data RAM cache. The non-critical words in the line fetched following the critical word are then written to the cache on a Dword basis, as they become available. Memory writes are posted to dual 4-Dwords (32-bit) memory write posting buffers. Write posts use the sequential addressing feature on the memory bus. With dual buffering, an out-of-sequence write will post to one write buffer while the other buffer is flushed to memory. There is one 8Dword read buffer in the MEM block. The buffer is used for both cacheable and non-cacheable memory space. Interrupt Controller The Interrupt Controller provides two interrupt channels to the ARM processor. One interrupt channel is presented to the ARM on its nFIQ and the other channel is presented on its nIRQ pin. These are referred to as the FIQ channel and the IRQ channel. Both channels operate in identical but independent fashion. The FIQ channel has a higher priority on the ARM processor than the IRQ channel. The Interrupt Controller includes a CONTROL register for each logical interrupt in the ARM Complex. The CONTROL register serves the following main purposes: * Provides the mapping between the EXT_INT inputs (physical interrupts) and the logical interrupt * Selects the particular type of signaling expected on the EXT_INT inputs: level, edge, active level high/low, etc. * Enables or disables a logical interrupt
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Digital Wireless Radio Interface
The CS22250 digital radio MAC I/F supports multiple radio baseband and RF interfaces. The baseband registers can be programmed during the configuration time using the control port interface. The MAC also provides the capability of programming the signal, service and length on a per packet basis without ARM intervention. This significantly improves the performance of the system.
There are three primary digital interface ports for the CS22250 that are used for configuration and during normal operation. These ports are: * The Control Port, which is used to configure, set power consumption modes, write and/or read the status of the radio base band registers * The TX Port, which is used to output the data that needs to be transmitted from the network processor * The RX Port, which is used to input the received demodulated data to the network processor
3.3
FEC Codec
The FEC codec performs Reed-Solomon code encoding to protect the data before it is transmitted to a noisy channel. It is a similar code as employed by the digital broadcast industry, such as ITU-T J.83 for DVB. The RS(255, 239) code implemented by the CS22250 can reduce error probability to 1/10e-9 in a typical 1/10e-3 error rate environment. The encoder/decoder can be programmed to vary the coding block length (N) and correctable error (t) to optimize the tradeoff between channel utilization and data protection. The range of N is currently set from 20 to 255, and the t is 8. The symbol size is fixed at 8 bits. Coding parameters can be set real time, allowing maximum flexibility for the system to adjust the FEC setting, such as block size, in order to optimize channel efficiency. The encoder also has a very low latency of two cycles. Both the encoder and decoder are fully pipelined in structure to achieve single cycle throughput. The FEC can be disabled in firmware.
3.4
High Speed Parallel Interface
This optional connectivity interface is the extension of the ARM control bus brought outside of the CS22250 chip. In order to reduce the pin count, address and data are multiplexed in a 32-bit address/data External Control Bus. For ease of connecting other devices to the CS22250, this bus runs at half the speed of the internal ARM control bus. The external control Bus interface exchanges data with the main memory via DMAC (DMA controller block). This functional block supports two DMA engines for full duplex operation. Moreover, one external interrupt pin is supported.
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Programmable Memory Controller
The CS22250 incorporates a general-purpose memory controller. The memory controller supports both SDRAM/async SRAM memory interface and a FLASH memory interface. In the RAM configuration, the system memory interface supports up to 4-Mbyte of 16-bit SDRAM running at frequency up to 103 MHz single-state access cycles or 256KB of 16 bit async SRAM. The memory controller provides programming of SDRAM parameters such as CAS latency, refresh rate etc; these registers are located in miscellaneous configuration registers. The CS22250 memory controller supports power saving feature of the SDRAM by toggling the Clock Enable (CKE) signal. When there are no pending memory requests from any internal requester, the CS22250 will keep CKE low to cause the SDRAM to stay in power down mode. Once a memory request is active, the CS22250 will assert CKE high to cause the SDRAM to come out of power down mode. Typicallythis can reduce memory power consumption by up to 50%. In ROM configuration, firmware for CS22250 is stored in non-volatile memory and is accessed through the Boot ROM interface. The maximum addressable ROM space supported is 1MB. ROM read/write and output enable are shared with RAM control pins.
3.6
Ethernet MAC Controller
The Ethernet MAC controller interface allows the Cirrus Logic CS22250 to provide connectivity to an Ethernet local area network. The controller can be used to interface with a cable or xDSL modem to share high speed internet multimedia and data traffic in a wireless home network. The Ethernet MAC controller is fully compliant with the IEEE 802.3 standard. The controller supports both half-duplex CSMA/CD and full-duplex operation at 10Mbps. The Ethernet MAC incorporates two power safe modes. The first disable mode disables the entire MAC core including clocks. The second is a partial sleep mode, which only disables transmit logic. In this mode, the entire MAC is powered upon receiving an Ethernet packet. The Ethernet MAC uses two independent DMA controllers to support full duplex operations with the system memory. The DMA controller is programmed and configured by the ARM.
3.7
USB Configuration Interface
The USB interface is a device interface that allows for bridge configuration from a USBenabled PC. Switching between normal and configuration modes is controlled by external logic.
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Pinout and Signal Descriptions
Figure 3. CS22250 Logical Pin Groupings
SMCLK nSMCS[1:0] System Memory Interface nSMRAS nSMCAS nSMWE SMDQM[1:0] SMCKE SMA[11:0] SMD[15:0] nBRCE nPERR, nSERR
EXT RESET CSS CSR WC_WiFi
CS22250 Controller
ETXCLK ERXCLK ERXDO ECOL ECRS ETXDO Ethernet 802.3 MAC I/F
TDO TDI TCK JTAG Interface TMS nTRST NTEST XTALIN Clock Interface XTALOUT XTRACLK PLLAGND PLL Power Interface PLLAVCC PLLDVCC PLLDGND PLLPLUS
ETXEN USBVP USBVM USB_ENUM
TXCLK TXPE TXD TXRDY CCA BBRNW nRESETBB BBAS nBBCS TXPAPE TXPEBB Digital Wireless Radio
OSAD[31:0] nOSWAIT OSRNW OSCLK nOSRESET OSCTLDIR OSREQ OSNINT DMA Interface DMAREQA DMAREQB
RXPEBB BBSCLK BBSDX SYNTHLE nRPD RXCLK MDRDY RXD
SPIO's
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This section provides detailed information on the CS22250 signals. The signal descriptions are useful for hardware designers who are interfacing the CS22250 with other devices.
System Memory Interface
The system memory interface supports standard SDRAM interface, Async SRAM and FLASH. There are a total of 37 signals in this interface. SMCLK Output System mem clock for SDRAM. Currently the interface supports 103 MHz for a maximum bandwidth of 200Mbytes/sec. nSMCS0 Output Chip select bit 0. This signal is used to select or deselect the SDRAM for command entry. When SMNCS is low it qualifies the sampling of nSMRAS, nSMCAS and nSMWE. Also, used as testmode(2) when NTEST pin is '0'. nSMCS1 Chip select bit 1. NBRCE Output Chip select for ROM access. This signal is used to select or deselect the boot ROM memory. Also used during reset to latch in the strap value for Ethernet; if set to a '1' implies Ethernet functional unit block is `enable'. NSMRAS Output Row address select. Used in combination with nSMCAS, nSMWE and nSMCS to specify which SDRAM page to open for access. Also used during reset to latch in the strap value for clk_bypass; if set to a '1' implies bypassing clock module; whatever clk is applied on the input clock is used for memclk and ctlclk. Also shared as the ROMOE signal. Output Column address select. Used in combination with nSMRAS, nSMWE and nSMCS to specify which piece of data to access in selected page. Also used during reset to latch in the strap value for same_freq; if set to a '1' implies internal mem_clk and arm_clk are running at the same frequency and 180 degrees out of phase. Output Write Enable. Used in combination with nSMRAS, nSMCAS, and nSMWE to specify whether the current cycle is a read or a write cycle. Also used during reset to latch in the strap value for tst_bypass; if set to a '1' implies PLL bypass. Also shared as the ROMWE to do flash programming. Output
NSMCAS
NSMWE
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SMDQM[1:0]
Output Data mask bit 1:0. These signals function as byte enable lines masking unwanted bytes on memory reads and write. Also used as testmode(1:0) when NTEST pin is '0'.
SMCKE
Output Clock enable. SMCKE is used to enable and disable clocking of internal RAM logic.
SMA0
Output Address bit0. The address bus specifies either the row address or column address. Also shared as boot-rom address bit0. This pin should have a pull-down.
SMA1
Output Address bit1. Also shared as boot-rom address bit1. This pin should have a pull-down.
SMA2
Output Address bit2. Also shared as boot-rom address bit2. This pin should have a pull-down.
SMA3
Output Address bit3. Also shared as boot-rom address bit3. Also used during reset to latch in the strap value for ossel; if set to a '1' implies optslot mode.
SMA4
Output Address bit4. Also shared as boot-rom address bit4. Also used during reset to latch in the strap value for romcfg. This pin should be pull down.
SMA5
Output Address bit5. Also shared as boot-rom address bit5. Also used during reset to latch in the strap value for test_rst_enb; if set to a '0' implies normal operation mode.
SMA6
Output Address bit6. Also shared as boot-rom address bit6. Also used during reset to latch in the strap value for freq_sel(0). Freq_sel(2:0) is used to select the multiplication factor for the internal PLL (000=1x and 111=8x).
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SMA7
Output Address bit7. Also shared as boot-rom address bit7. Also used during reset to latch in the strap value for freq_sel(1). Freq_sel(2:0) is used to select the multiplication factor for the internal PLL (000=1x and 111=8x).
SMA8
Output Address bit8. Also shared as boot-rom address bit8. Also used during reset to latch in the strap value for freq_sel(2). Freq_sel(2:0) is used to select the multiplication factor for the internal PLL (000=1x and 111=8x).
SMA9
Output Address bit9. Also shared as boot-rom address bit9. Also used during reset to latch in the strap value for sdram_delay(0). Sdram_delay(2:0) is used to select the delay factor for the internal memory clock (000=0ns and 111=1.75ns with each .25ns increments).
SMA10
Output Address bit10. Also shared as boot-rom address bit10. Also used during reset to latch in the strap value for sdram_delay(1). Sdram_delay(2:0) is used to select the delay factor for the internal memory clock (000=0ns and 111=1.75ns with each .25ns increments).
SMA11
Output Address bit11. Also shared as boot-rom address bit11. Also used during reset to latch in the strap value for sdram_delay(2). Sdram_delay(2:0) is used to select the delay factor for the internal memory clock (000=0ns and 111=1.75ns with each .25ns increments).
SMD[7:0]
Bidirectional Data bus. The data bus contains the data to be written to memory on a write cycle and the read return data on a read cycle.
SMD[15:8]
Bidirectional Shared data bus. The data bus contains the data to be written to RAM memory on a write cycle and the read return data on a read cycle. Data bit [15:8] is also shared as boot ROM address bit [19:12].
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Digital Wireless Radio Interface
All Radio input buffers are Schmitt triggered input buffers. There are a total of 25 signals in this interface. TXCLK Input Transmit clock is a clock input from the radio baseband processor. This signal is used to clock out the transmit data on the rising edge of TXCLK. TXPEBB Output Baseband transmit power enable is an output from the MAC to the radio baseband processor. When active, the baseband processor transmitter is configured to be operational, otherwise the transmitter is in standby mode. TXD Output It is the serial data output from the MAC to the radio baseband processor. The data is transmitted serially with the LSB first. The data is driven by the MAC on the rising edge of TXCLK and is sampled by the radio baseband processor on the falling edge of TXCLK and rising edge of TXCLK. TXRDY Input Transmit data ready is an input to the MAC from the radio baseband processor to indicate that the radio baseband processor is ready to receive the data packet over the TXD signal. The signal is sampled by the MAC on the rising edge of TXCLK. CCA Input Clear channel assessment is an input from the radio baseband processor to signal that the channel is clear to transmit. When this signal is a 0, the channel is clear to transmit. When this signal is a 1, the channel is not clear to transmit. This helps the MAC to determine when to switch from receive to transmit mode. BBRNW Output Baseband read/write is an output from the MAC to indicate the direction of the SD bus when used for reading or writing data. This signal has to be setup to the rising edge of BBSCLK for the baseband processor and is driven on the falling edge of BBSCLK. NRESETBB Output Baseband reset is an output of the MAC to reset the baseband processor.
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BBAS
Output Baseband address strobe is used to envelop the address or the data on the BBSDX bus. A logic 1 envelops the address and a logic 0 envelops the data. This signal has to be setup to the rising edge of BBSCLK for the baseband processor and is driven on falling edge of BBSCLK.
NBBCS
Output Baseband chip select is an active low output to activate the serial control port. When inactive, the SD, BBSCLK, BBAS and BBRNW signals are `don't cares'.
TXPAPE
Output Radio power amplifier power enable is a software controlled output. This signal is used to gate power to the power amplifier.
TXPE
Output Radio transmit power enable indicates if transmit mode is enabled. When low, this signal indicates receive mode.
RXPEBB
Output Baseband receive power enable is an output that indicates if the MAC is in receive mode. A output signal to baseband processor enables receive mode in baseband processor.
BBSCLK
Output Baseband serial clock is a programmable output generated by dividing ARM_CLK by 14 (default). This clock is used for the serial control port to sample the control and data signals.
BBSDX
Bi-directional Baseband serial data is a bi-directional serial data bus, which is used to transfer address and data to/from the internal registers of the baseband processor.
SYNTHLE
Output Synthesizer latch enable is an active high signal used to send data to the synthesizer. (Use with modular Cresta II Modular Radio only).
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NRPD
Output Radio power down enable. This active low signal is used for power management purposes for the radio circuitry.
RXCLK
Input This is an input from base band processor. It is used to clock in received data from base band processor.
MDRDY
Input Receive data ready is an input signal from the baseband processor, indicating a data packet is ready to be transferred to the MAC. The signal returns to inactive state when there is no more receiver data or when the link has been interrupted. This signal is sampled on the falling edge of RXCLK and sampled at rising edge of RXCLK.
RXD
Input Receive data is an input from the baseband processor transferring demodulated header information and data in a serial format. The data is frame aligned with MD_RDY. This signal is sampled on the falling edge of RXCLK and sampled at rising edge of RXCLK.
DACAVCC Analog power for DAC. 3.3V. DACAGND Analog ground for DAC. RLQ
Input
Input
Output Radio link quality is based on packet error rate. Active low implies packet received without errors. Note: lost packets arenot detected.
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PLL and Clock Interface
There are three clock pins and five PLL power pins for a total of 8 signals in this interface.
XTAL_CLKIN 44 MHz Reference clock input/crystal clock input. XTALOUT Reference crystal clock output.
Input
Output
XTRACLK
Input Second clock input to clock module. Use depending on clock module configuration setting. Refer to the clock section for more information.
PLLAGND Analog PLL ground. PLLAVCC Analog PLL power. 3.3V input. PLLDGND Digital PLL ground. PLLDVCC Digital PLL power. This is 1.8V input. PLLPLUS Analog PLL ground.
Input
Input
Input
Input
Input
Ethernet Interface
ETXCLK Input Transmit clock. A 10 MHz clock input. This clock signal provides the reference sampling point for transmit data. ETXDOOutput Transmit data. This output signal is NRZ formatted and is transmitted to the Ethernet PHY layer.
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ETXEN
Output Transmit enable. This signal is synchronous to ETXCLK. It enables data transmission.
ECOL
Input Collision signal. This input signal indicates whether a collision occurred in the network.
ECRS
Input Carrier detect. An input from the PHY layer thatindicates there is activity in the network.
ERXCLK
Input Receive clock. This is the reference receive clock from the PHY layer.
ERXDO Receive data. It is synchronized with receive clock.
Input
System Reset
EXT_RESET Input The system must place the RESET signal in a high-Z state during card power up. The signal must remain high impedance for at least 1 msec after Vcc becomes valid. CSS (Clear Settings Set) Network security ID reset request. Input
CSR (Clear Settings Reset) Network security ID reset successful.
Output
External Control Bus
OSAD[31:0] Bi-directional Multiplexed address and data bus on the external control bus to a shared 32-bit bus on the external control bus. Also, de-multiplexing of the data from external control bus to the internal control bus.
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NOSWAIT
Input The wait bus is a single bit bus, which indicates the processing element addressed on the external control address space is not capable of completing the transfer on this cycle.
OSRNW External control bus read/write. OSCLK
Output
Output External control bus clock. This clock is half the frequency of the internal control clock. External processing element clocks the input data to the OSAD bus on this clock edge.
NOSRESET External control bus reset. OSCTLDIR
Output
Output External control bus direction control. The direction bus is a single bit bus, which indicates the direction of the tri-state drivers on the address/data bus. A logic `0' on this bus indicates the tri-state drivers are on source mode on the OS bus and a logic `1' on this bus indicates the tri-state drivers are on receive mode from the OS bus.
OSREQ
Output External control bus request. It indicates a transfer has been initiated, addressed to the external control bus address space. The external control bus FUB shall de-assert the transfer request on the next OS cycle, if the OS wait signal is not asserted by the processing element on the OS bus during the data phase.
OSNINT This is the interrupt for external bus interface to the ARM core.
Input
External DMA Interface
DMAREQA Input DMA request channel A. When driven HIGH, this signal tells the DMA controller that an agent on the external control bus is requesting a DMA access. Input DMA request channel B. When driven HIGH, this signal tells the DMA controller that an agent on the external control bus is requesting a DMA access.
DMAREQB
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Debug Interface
TDO Test data output. TDI Test data input. This input has integral pull-up. TCK Test clock signal. TMS Test mode select. This input has integral pull-up. Input Input Input Output
NTRST Test interface reset. This input has integral pull-up.
Input
USB Interface
USBVP Bi-directional Differential USB data plus. For high-speed mode, this signal is pull up to 5 volt during IDLE state (see USB_ENUM).
USBVM Differential USB data minus. USB_ENUM
Bi-directional
Output USB Enumeration. Indicates disconnect/connect event. USB_ENUM is used to pull the D+ line high, indicating to the host or hub a USB bus "full rate" connection is active.
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Miscellaneous Interface
RSVD_0:2 (SPIO) Bi-directional Special Purpose I/O reserved for supporting custom interfaces. * Check with Cirrus Logic support for supported options and usage.
NTEST
Input Chip test mode pin. Used in conjunction with SMNCS0, SMDQM[0:1]. Pull up for normal operation.
WC_WiFi
Input External Dual MAC mode switch control signal. Use for hardware switching between Whitecap2 Wi-Fi (802.11b) and multimedia modes. (WiFi = low).
Power and Ground
VCC (5V and 3.3V)
1
Input 5V inputs. There are a total of 3 pins.
VDD (3.3V) 3.3V inputs. There are a total of 20 pins. VEE (1.8V) 1.8 inputs to the core. There are a total of 9 pins. VSS Ground. There are a total of 27 pins.
1
Input
Input
Input
5V or 3.3V depending on desired configuration.
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Figure 4. CS22250 208 pin FPBGA Pinout Diagram
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DS551PP2
Rev. 3.0
Table 1. Pin Listing by Name ball H17 K17 H15 J16 H14 T04 C16 U05 P06 D11 C13 D12 B12 A06 A02 C04 A03 B05 A05 A04 H01 G15 A07 A13 B08 C03 C07 C08 C12 R05 T06 L15 G14 K14 C11 D03 E04 D04 R03 R01 P02 N01 N02 D02 C01 name BBAS BBNCS BBRNW BBSCLK BBSDX CAL/C3CS CCA CSR CSS DACAVDD DACAVSS RSVD RSVD ECOL ECRS ERXCLK ERXD0 ETXCLK ETXD0 ETXEN EXT_RESET MDRDY N/C N/C N/C N/C N/C N/C N/C N/C N/C NBRCE NRESETBB NTEST NTRST OSAD00 OSAD01 OSAD02 OSAD03 OSAD04 OSAD05 OSAD06 OSAD07 OSAD08 OSAD09 ball B02 L04 P03 P01 N03 N04 E01 E03 E02 H02 G04 F01 G01 F02 K03 R02 L01 M02 M03 M04 K02 F03 G03 D01 U01 T03 L02 C02 L03 H03 G02 A16 D14 B15 A17 A15 F15 B16 B03 D05 U04 P05 G17 F14 F17 name OSAD10 OSAD11 OSAD12 OSAD13 OSAD14 OSAD15 OSAD16 OSAD17 OSAD18 OSAD19 OSAD20 OSAD21 OSAD22 OSAD23 OSAD24 OSAD25 OSAD26 OSAD27 OSAD28 OSAD29 OSAD30 OSAD31 OSCLK OSCTLDIR OSDMAREQ0 OSDMAREQ1 OSNINT OSNRESET OSNWAIT OSREQ OSRNW PLLAGND PLLAVCC PLLDGND PLLDVCC PLLPLUS RLQ RNPD RSVD RSVD_0 RSVD_1 RSVD_2 RXCLK RXD RXPEBB ball T16 U17 P14 T17 R17 P15 N14 P17 N15 M14 M16 M15 U07 U11 T08 R10 P11 T11 R11 P12 R12 P13 U12 R13 U13 U14 R14 U15 U16 R15 U06 T07 P08 R06 P07 L16 L14 U03 P04 J17 A10 B10 C10 D10 D17 name SMA00 SMA01 SMA02 SMA03 SMA04 SMA05 SMA06 SMA07 SMA08 SMA09 SMA10 SMA11 SMCKE SMCLK SMD00 SMD01 SMD02 SMD03 SMD04 SMD05 SMD06 SMD07 SMD08 SMD09 SMD10 SMD11 SMD12 SMD13 SMD14 SMD15 SMDQM00 SMDQM01 SMNCAS SMNCS00 SMNCS01 SMNRAS SMNWE SYNTH_LE1 SYNTH_LE2 SYNTHLE TCK TDI TDO TMS TXCLK ball D15 E16 B17 E15 D16 E14 B06 D06 A01 J01 T02 A12 B04 B11 B14 C06 C15 D09 E17 F04 G16 J15 K01 N17 P16 R04 R08 T01 T10 T12 T14 U09 A09 C09 D07 J03 J04 J14 K16 R09 T09 A08 A11 A14 B01 name TXD TXPAPE TXPE TXPEBB TXRDY USB_ENUM USBVM USBVP VCC VCC VCC VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VEE VEE VEE VEE VEE VEE VEE VEE VEE VSS VSS VSS VSS Rev. 3.0
CS22250 Wireless 10BT Controller
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DS551PP2
ball B07 B09 C05 C17 D08 F16 H04
name VSS VSS VSS VSS VSS VSS VSS
ball H16 J02 K04 K15 L17 M01 M17
name VSS VSS VSS VSS VSS VSS VSS
ball N16 P09 P10 R07 R16 T13 T15
name VSS VSS VSS VSS VSS VSS VSS
ball U02 U08 U10 T05 C14 D13 B13
name VSS VSS VSS WC_WiFi XTALCLKIN XTALOUT XTRACLK
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DS551PP2
Rev. 3.0
Table 2. Pin Listing by Ball ball A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 name VCC ECRS ERXD0 ETXEN ETXD0 ECOL N/C VSS VEE TCK VSS VDD N/C VSS PLLPLUS PLLAGND PLLDVCC VSS OSAD10 RSVD VDD ETXCLK USBVM VSS N/C VSS TDI VDD RSVD XTRACLK VDD PLLDGND RNPD TXPE OSAD09 OSNRESET N/C ERXCLK VSS VDD N/C N/C VEE TDO NTRST ball C12 C13 C14 C15 C16 C17 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 E01 E02 E03 E04 E14 E15 E16 E17 F01 F02 F03 F04 F14 F15 F16 F17 G01 G02 G03 G04 G14 G15 name N/C DACAVSS XTALCLKIN VDD CCA VSS OSCTLDIR OSAD08 OSAD00 OSAD02 RSVD_0 USBVP VEE VSS VDD TMS DACAVDD RSVD XTALOUT PLLAVCC TXD TXRDY TXCLK OSAD16 OSAD18 OSAD17 OSAD01 USB_ENUM TXPEBB TXPAPE VDD OSAD21 OSAD23 OSAD31 VDD RXD RLQ VSS RXPEBB OSAD22 OSRNW OSCLK OSAD20 NRESETBB MDRDY ball G16 G17 H01 H02 H03 H04 H14 H15 H16 H17 J01 J02 J03 J04 J14 J15 J16 J17 K01 K02 K03 K04 K14 K15 K16 K17 L01 L02 L03 L04 L14 L15 L16 L17 M01 M02 M03 M04 M14 M15 M16 M17 N01 N02 N03 name VDD RXCLK EXT_RESET OSAD19 OSREQ VSS BBSDX BBRNW VSS BBAS VCC VSS VEE VEE VEE VDD BBSCLK SYNTHLE VDD OSAD30 OSAD24 VSS NTEST VSS VEE BBNCS OSAD26 OSNINT OSNWAIT OSAD11 SMNWE NBRCE SMNRAS VSS VSS OSAD27 OSAD28 OSAD29 SMA09 SMA11 SMA10 VSS OSAD06 OSAD07 OSAD14 ball N04 N14 N15 N16 N17 P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 P15 P16 P17 R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 T01 T02 T03 T04 T05 T06 name OSAD15 SMA06 SMA08 VSS VDD OSAD13 OSAD05 OSAD12 SYNTH_LE2 RSVD_2 CSS SMNCS01 SMNCAS VSS VSS SMD02 SMD05 SMD07 SMA02 SMA05 VDD SMA07 OSAD04 OSAD25 OSAD03 VDD N/C SMNCS00 VSS VDD VEE SMD01 SMD04 SMD06 SMD09 SMD12 SMD15 VSS SMA04 VDD VCC OSDMAREQ1 CAL/C3CS WC_WiFi N/C Rev. 3.0
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DS551PP2
ball T07 T08 T09 T10 T11 T12 T13
name SMDQM01 SMD00 VEE VDD SMD03 VDD VSS
ball T14 T15 T16 T17 U01 U02 U03
name VDD VSS SMA00 SMA03 OSDMAREQ0 VSS SYNTH_LE1
ball U04 U05 U06 U07 U08 U09 U10
name RSVD_1 CSR SMDQM00 SMCKE VSS VDD VSS
ball U11 U12 U13 U14 U15 U16 U17
name SMCLK SMD08 SMD10 SMD11 SMD13 SMD14 SMA01
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DS551PP2
Rev. 3.0
5
Specifications
Table 3. Absolute Maximum Ratings Symbol VEE VDD VIN IIN TSTGP Parameter Voltage at Core DC Supply ( I/O) Input Voltage DC Input Current Storage Temperature Range Limits -0.18 to 2.0 -0.3 to 3.9 -0.1 to Vdd + 0.3 +/- 10 -40 to 125 Units V V V A C
Table 4. Recommended Operating Conditions Symbol VDD Vee XTALIN FTCK TA TJ Parameter DC Supply Input frequency JTAG clock frequency Ambient Temperature Junction Temperature Limits 3.15 to 3.60 (3V I/O) 1.6 to 2.0 (core) 44 or 48 0 to 10 0 to +70 0 to +105 Units V MHz MHz C C
Notes: 1. The XTALIN & XTALOUT pins have minimal ESD protection. 2. This device may have ESD sensitivity above 500V HBM per JESD22-A114. Normal ESD precautions need to be followed.
Table 5. Capacitance Symbol CIN COUT Parameter Input Capacitance Output Capacitance Value 3.4 4.0 Units pF pF
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DS551PP2
Rev. 3.0
Table 6. DC Characteristics Symbol VIL VIH VOL VOH IIL IOZ IDD IEE Parameter Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Input Leakage Current 3-State Output Leakage Current Dynamic Supply Current Note 1 Condition Min -0.50 0.7 * VDD VSS - 0.1 -10 -10 22 123 Typ. Max Units 0.3 * VDD V VDD + 0.3 V V VSS + 0.1 V 10 A 10 A mA
IOL = 800 A IOH = 800 A VIN = VSS or VDD VOH = VSS or VDD VDD = 3.3V VDD = 1.8V
5.1
AC Characteristics and Timing
Table 7. System Memory Interface Timings Parameter tdSMD tdSMA tdSMDQM tdSMNCS tdSMNWE tdSMCKE tdSMNCAS tdSMNRAS TperSMCLK TsuSMD ThSMD
Notes: 1. 2.
Parameter Description SMCLK to SMD[31:0] output delay SMCLK to SMA[11:0] output delay SMCLK to SMDQM[3:0] output delay SMCLK to SMNCS[1:0] output delay SMCLK to SMNWE output delay SMCLK to SMCKE output delay SMCLK to SMNCAS output delay SMCLK to SMNRAS output delay SMCLK period SMD[31:0] setup to SMCLK SMD[31:0] hold from SMCLK
Min
72 1.0 2.4
Max 7 4.7 5.1 4.1 4.5 4.3 4.0 5.0 103
Units ns ns ns ns ns ns ns ns ns ns ns
Outputs are loaded with 35pf on SMD, 25pf on SMA, SMDQM, SMNRAS, and SMNCAS and 20pf on SMCLK, SMNCS, and SMCKE. An attempt has been made to balance the setup time needed by the SDRAM and the setup needed by CS22210 to read data. If there is a problem meeting setup on the SDRAM, there is a programmable delay line on SMCLK which can help meet the setup time. Care must be taken, however, not to violate the setup on the return read data. The delay can be increased by a multiple of 0.25ns by using the SMA[11:09] pins to selectively set the clock delay.
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DS551PP2
Rev. 3.0
SMCLK
tdSMD
SMD[15:0]
WRITE DATA tdSMA ROW ADDR COLUMN ADDR tdSMDQM
SMA[13:0]
SMDQM[1:0]
tdSMNCS
SMNCS[1:0]
tdSMNWE
SMNWE
tdSMCKE
SMCKE
tdSMNRAS
SMNRAS
tdSMNCAS
SMNCAS
Figure 5. System Memory Interface `Write' Timing Diagram
tperSMCLK
SMCLK
thSMD tsuSMD
SMD[15:0]
DATA tdSMA
ROW ADDR
SMA[13:0] SMDQM[1:0]
COLUMN ADDR
tdSMNCS
SMNCS[1:0] SMNWE
ACTIVE tdSMCKE
SMCKE
tdSMNRAS
SMNRAS
tdSMNCAS
SMNCAS
Figure 6. System Memory Interface 'Read' Timing Diagram
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DS551PP2
Rev. 3.0
Table 8. ROM/Flash Memory Read Timing Item Clock Period
(1) (2) (3)
Symbol tperSMCLK tid SMD tf SMRAS tACC td SMA td BRCE td SMRAS tsu SMD th SMD 1.0 ns 2.4 ns
(4)
Min 72 MHz 6(tperSMCLK)
CE to SMD Latched Data
Max 103 MHz 221 ns 220 ns 4.0 ns 4.5 ns 5.0 ns
OE de-asserted to OE asserted ROM address to output delay SMCLK to SMA output delay
SMCLK to BRCE output delay (CE) SMCLK to SMRAS output delay (OE) SMD setup to SMCLK SMD hold from SMCLK
1. The memclock timing is derived by bootstrap PLL settings. Synchronous modes at 77 MHz & 72 MHz are currently supported. 2. tid SMD is based on the fm_romrdlat register settings - default is 09h max. (77Mhz ~ 17 times SMCLK = 221ns). 3. tf SMRAS is the minimum time required before the next OE is active on the bus (6 times SMCLK). The ROM device must release the bus within this time frame (77MHz ~ 78 ns). 4. Based on default fm_romrdlat register settings (note: 09h translates to 11h) see fm_romrdlat register settings for more information.
SMCLK tper SMCLK
t ld
SMD
tf
SMRAS
t ACC
SMD[7:0]
tsu
SMD
th
SMD
DATA td
SMA
SMA[11:0], SMD[13:8]
ADDRESS
SMNWE
td
BRCE (CE)
BRCE
td
SMRAS
BRCE
td
SMRAS (OE)
td
SMRAS
Figure 7. ROM Memory Interface 'Read' Timing Diagram
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DS551PP2
Rev. 3.0
Table 9. USB Interface Timings Parameter USBVPX USBVPM Description Differential data positive Differential data negative Min 4 4 Max 20 20 Units ns ns
Table 10. Radio MAC AC Timings - Intersil Modes Parameter tdBBAS tdBBRNW tdnBBCS tdBBSDX TsuBBSDX ThBBSDX tdTXD tdTXD TsuRXD ThRXD TsuMDRDY ThMDRDY tdTXPEBB tdRXPEBB TsuTXRDY ThTXRDY 2 TdutyRXCLK 2 TdutyTXCLK
Notes: 1. 2. 3.
Parameter Description BBAS output delay from falling BBSCLK BBRNW output delay from falling BBSCLK nBBCS output delay from falling BBSCLK BBSDX output delay from falling BBSCLK BBSDX setup to rising edge of BBSCLK BBSDX hold from rising edge of BBSCLK TXD output delay from rising TXCLK (SMAC Mode) TXD output delay from rising TXCLK (RMAC Mode) RXD setup to rising edge of RXCLK RXD hold from rising edge of RXCLK MDRDY setup to falling edge of RXCLK MDRDY hold from falling edge of RXCLK TXPEBB output delay from rising TXCLK RXPEBB output delay from rising RXCLK TXRDY setup to falling edge of TXCLK TXRDY hold from falling edge of TXCLK RXCLK period TXCLK period
Min
Max 8.2 8.0 59.0 7.0
14.8 0.0 33.5 15.4 1.0 1.8 2 1 15.0 16.0 6.5 0 See Note See Note
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4.
5.
CCA signal is double synchronized to ARMCLKIN. ARMCLK must be at least 4 times the TXCLK and RXCLK frequency. Harris baseband (3824/3824A) generates RXCLK and TXCLK of 4 Mhz. the duty cycle varies between 33-40% with a high time of 90.9ns and low time that alternates between 136 and 182ns. The clock period varies between 227 and 272 ns, giving an effective period of 250ns. TXD delay in 802.11b mode is the result of sampling the TXCLK with the ctlclk, therefore the maximum delay is equal to two ctlclk periods plus the flop-to-output delay. In this table, ctlclk is assumed to have a 13 ns period. BBNCS output delay = [(1/ARMCLK freq)*ceiling(SER_CLK_DIV/2)] + 7ns, the specified value is based on ARMCLK of 77 Mhz and SER_CLK_DIV=8.
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DS551PP2
Rev. 3.0
Table 11. Radio MAC AC Timings - RFMD Modes Parameter tdBBRNW tdnBBCS tdBBSDX TsuBBSDX ThBBSDX tdTXD tdTXD TsuRXD ThRXD TsuMDRDY ThMDRDY tdTXPEBB tdRXPEBB TsuTXRDY ThTXRDY
Notes: 1. 2. 3.
Parameter Description BBRNW output delay from falling BBSCLK nBBCS output delay from falling BBSCLK BBSDX output delay from falling BBSCLK BBSDX setup to rising edge of BBSCLK BBSDX hold from rising edge of BBSCLK TXD output delay from rising TXCLK (SMAC Mode) TXD output delay from rising TXCLK (RMAC Mode) RXD setup to rising edge of RXCLK RXD hold from rising edge of RXCLK MDRDY setup to falling edge of RXCLK MDRDY hold from falling edge of RXCLK TXPEBB output delay from rising TXCLK RXPEBB output delay from rising RXCLK TXRDY setup to falling edge of TXCLK TXRDY hold from falling edge of TXCLK
Min
Max 6.7 110.79 7.0
14.5 0.0 33.5 15.4 1.0 1.8 2 1 15.0 16.0 6.5 0
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4.
CCA signal is double synchronized to ARMCLKIN. ARMCLK must be at least 4 times the TXCLK and RXCLK frequency. TXD delay in 802.11b mode is the result of sampling the TXCLK with the ctlclk, therefore the maximum delay is equal to two ctlclk periods plus the flop-to-output delay. In this table, ctlclk is assumed to have a 13 ns period. BBNCS output delay = [(1/ARMCLK freq)*ceiling(SER_CLK_DIV/2)] + 7ns, the specified value is based on ARMCLK of 77 Mhz and SER_CLK_DIV=8.
Table 12. Package Specifications Symbol JC JA TJ_MAX
Notes: 1. ARMCLK / MEMCLK = 77MHz
Parameter Junction-to-Case Thermal Resistance Junction-to-Open Air Thermal Resistance Max Junction Temperature
Value 2.5 26.9 105
Units C/W C/W C
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DS551PP2
Rev. 3.0
6
Packaging
The CS22250 controller is available in a 208 Fine Pitch Ball Grid Array (FPBGA) package. Figure 8 contains the package mechanical drawing. Figure 8. CS22250 FPBGA-pin Mechanical Drawing
CS22250 Wireless 10BT Controller
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DS551PP2
Rev. 3.0

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